C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

Table 16.1. AC Parameters for External Memory Interface

Parameter

TSYSCLK

TACS

TACW

TACH

TALEH

TALEL

TWDS

TWDH

TRDS

TRDH

Description

System Clock Period

Address/Control Setup Time

Address/Control Pulse Width

Address/Control Hold Time

Address Latch Enable High Time

Address Latch Enable Low Time

Write Data Setup Time

Write Data Hold Time

Read Data Setup Time

Read Data Hold Time

Min

40

0

1 x TSYSCLK

0

1 x TSYSCLK

1 x TSYSCLK

1 x TSYSCLK

0

20

0

Max

—

3 x TSYSCLK

16 x TSYSCLK

3 x TSYSCLK

4 x TSYSCLK

4 x TSYSCLK

19 x TSYSCLK

3 x TSYSCLK

—

—

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

202

Rev. 1.5

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