C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

17.1.6. External Memory Interface Pin Assignments

If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.5)

should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and, if

the External Memory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Cross-

bar Decode Table with EMIFLE=1 and the EMIF in Multiplexed mode. Figure 17.5 shows an example

Crossbar Decode Table with EMIFLE=1 and the EMIF in Non-multiplexed mode.

If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the

External Memory Interface will control the output states (logic 1 or logic 0) of the affected Port pins during

the execution phase of the MOVX instruction, regardless of the settings of the Crossbar registers or the

Port Data registers. The output configuration (push-pull or open-drain) of the Port pins is not affected by

the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus.

In most cases, GPIO pins used in EMIF operations (especially the /WR and /RD lines) should be

configured as push-pull and ‘parked’ at a logic 1 state. See Section “16. External Data Memory

Interface and On-Chip XRAM” on page 187 for more information about the External Memory Interface.

P0

P1

P2

P3

Crossbar Register Bits

PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

TX0

z

RX0

z

UART0EN: XBR0.2

SCK

z

z

MISO

MOSI

zz

zz

SPI0EN: XBR0.1

NSS

z

z

NSS is not assigned to a port pin when the SPI is placed in 3-wire mode

SDA

z zzz

SCL

z zz

zz

zzz

SMB0EN: XBR0.0

TX1

z

zzz

RX1

z zz

zzzz

zzzzz

UART1EN: XBR2.2

CEX0

z

zzz

zzzzzz

CEX1

z zz

zzzzzzz

CEX2

CEX3

z

z

z

zzzzzzzz

zzzzzzzzz

PCA0ME: XBR0.[5:3]

CEX4

z

zzzzzzzzz

CEX5

z zzzzzzzzz

ECI

zzzzz

zzzzzzzzzzzz

ECI0E: XBR0.6

CP0

zzzzz

zzzzzzzzzzzzz

CP0E: XBR0.7

CP1

zzzzz

zzzzzzzzzzzzzz

CP1E: XBR1.0

CP2

zzzzz

zzzzzzzzzzzzzzz

CP2E: XBR3.3

T0

zzzzz

zzzzzzzzzzzzzzzz

T0E: XBR1.1

/INT0

zzzzz

zzzzzzzzzzzzzzzzz

INT0E: XBR1.2

T1

zzzzz

zzzzzzzzzzzzzzzzzz

T1E: XBR1.3

/INT1

zzzzz

zzzzzzzzzzzzzzzzzzz

INT1E: XBR1.4

T2

zzzzz

zzzzzzzzzzzzzzzzzzzz

T2E: XBR1.5

T2EX

zzzzz

zzzzzzzzzzzzzzzzzzzzz

T2EXE: XBR1.6

T3

zzzzz

zzzzzzzzzzzzzzzzzzzzzz

T3E: XBR3.0

T3EX

zzzzz

zzzzzzzzzzzzzzzzzzzzzzz

T3EXE: XBR3.1

T4

zzzzz

zzzzzzzzzzzzzzzzzzzzzzzz

T4E: XBR2.3

T4EX

zzzzz

zzzzzzzzzzzzzzzzzzzzzzzz

T4EXE: XBR2.4

/SYSCLK z z z z z

z z z z z z z z z z z z z z z z z z z z z z z z SYSCKE: XBR1.7

CNVSTR0 z z z z z

z z z z z z z z z z z z z z z z z z z z z z z z CNVSTE0: XBR2.0

CNVSTR2 z z z z z

z z z z z z z z z z z z z z z z z z z z z z z z CNVSTE2: XBR3.2

AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data

Figure 17.4. Priority Crossbar Decode Table

(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF)

208

Rev. 1.5

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