C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

17. Port Input/Output

The C8051F04x family of devices are fully integrated mixed-signal System on a Chip MCUs with 64 digital

I/O pins (C8051F040/2/4/6) or 32 digital I/O pins (C8051F041/3/5/7), organized as 8-bit Ports. All ports are

both bit- and byte-addressable through their corresponding Port Data registers. All Port pins are 5 V-toler-

ant, and all support configurable Open-Drain or Push-Pull output modes and weak pullups. A block dia-

gram of the Port I/O cell is shown in Figure 17.1. Complete Electrical Specifications for the Port I/O pins

are given in Table 17.1.

/WEAK-PULLUP

PUSH-PULL

/PORT-OUTENABLE

PORT-OUTPUT

VDD

VDD

(WEAK)

PORT

PAD

ANALOG INPUT

PORT-INPUT

Analog Select

(Ports 1, 2, and 3)

DGND

Figure 17.1. Port I/O Cell Block Diagram

Table 17.1. Port I/O DC Electrical Characteristics

VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max Units

Output High Voltage

(VOH)

IOH = –3 mA, Port I/O Push-Pull

IOH = –10 µA, Port I/O Push-Pull

IOH = –10 mA, Port I/O Push-Pull

VDD – 0.7

—

—

VDD – 0.1

—

—

—

VDD – 0.8

—

V

Output Low Voltage

(VOL)

IOL = 8.5 mA

IOL = 10 µA

IOL = 25 mA

—

—

0.6

—

—

0.1

V

—

1.0

—

Input High Voltage (VIH)

0.7 x VDD

—

—

Input Low Voltage (VIL)

—

—

0.3 x VDD

DGND < Port Pin < VDD, Pin Tri-state

—

Input Leakage Current Weak Pullup Off

—

Weak Pullup On

—

—

—

—

±1

µA

10

—

Input Capacitance

—

5

—

pF

Rev. 1.5

203

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