C8051F045 查看數據表（PDF） - Silicon Laboratories
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C8051F045 Datasheet PDF : 328 Pages
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C8051F040/1/2/3/4/5/6/7
The C8051F04x family of devices have a wide array of digital resources which are available through the
four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a Gen-
eral-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for
example), as shown in Figure 17.2. The system designer controls which digital functions are assigned
pins, limited only by the number of pins available. This resource assignment flexibility is achieved through
the use of a Priority Crossbar Decoder. The state of a Port I/O pin can always be read from its associated
Data register regardless of whether that pin has been assigned to a digital peripheral or behaves as GPIO.
The Port pins on Ports 1, 2, and 3 can be used as Analog Inputs to ADC2 (C8051F040/1/2/3 only), Analog
Voltage Comparators, and ADC0, respectively.
Highest
Priority
Lowest
Priority
Port
Latches
UART0
2
4
SPI
2
SMBus
2
UART1
6
PCA
Comptr.
2
Outputs
T0, T1,
T2, T2EX,
T3, T3EX,
8
T4,T4EX,
/INT0,
/INT1
/SYSCLK
CNVSTR0
CNVSTR2
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
8
P2 (P2.0-P2.7)
8
P3 (P3.0-P3.7)
XBR0, XBR1, XBR2,
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
Priority
Decoder
8
Digital
Crossbar
8
P0
I/O
Cells
P1
I/O
Cells
8
P2
I/O
Cells
8
P3
I/O
Cells
To External
Memory
Interface
(EMIF)
To
ADC2
Input
To
Comparators
To
ADC0
Input
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Lowest
Priority
Figure 17.2. Port I/O Functional Block Diagram
An External Memory Interface, which is active during the execution of an off-chip MOVX instruction, can be
active on either the lower Ports or the upper Ports. See Section “16. External Data Memory Interface
and On-Chip XRAM” on page 187 for more information about the External Memory Interface.
17.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to
the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port
pins are allocated in order starting with P0.0 and continue through P3.7, if necessary. The digital peripher-
als are assigned Port pins in a priority order which is listed in Figure 17.3, with UART0 having the highest
priority and CNVSTR2 having the lowest priority.
204
Rev. 1.5
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