C8051F045 查看數據表（PDF） - Silicon Laboratories
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C8051F045 Datasheet PDF : 328 Pages
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C8051F040/1/2/3/4/5/6/7
1.9. 8-Bit Analog to Digital Converter (C8051F040/1/2/3 Only)
The C8051F040/1/2/3 devices have an on-board 8-bit SAR ADC (ADC2) with an 8-channel input multi-
plexer and programmable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-
bit performance with an INL of ±1LSB. Eight input pins are available for measurement and can be pro-
grammed as single-ended or differential inputs. The ADC is under full control of the CIP-51 microcontroller
via the Special Function Registers. The ADC2 voltage reference is selected between the analog power
supply (AV+) and an external VREF pin. On C8051F040/2 devices, ADC2 has its own dedicated VREF2
input pin; on C8051F041/3 devices, ADC2 shares the VREFA input pin with the 12/10-bit ADC0. User soft-
ware may put ADC2 into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful
when different ADC input channels have widely varied input voltage signals, or when it is necessary to
"zoom in" on a signal with a large dc offset (in differential mode, a DAC could be used to provide the dc off-
set). The PGA gain can be set in software to 0.5, 1, 2, or 4.
A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands,
timer overflows, or an external input signal. ADC2 conversions may also be synchronized with ADC0 soft-
ware-commanded conversions. Conversion completions are indicated by a status bit and an interrupt (if
enabled), and the resulting 8-bit data word is latched into an SFR upon completion.
Analog Multiplexer
Configuration, Control, and Data Registers
AIN2.0
AIN2.1
AIN2.2
AIN2.3
AIN2.4
AIN2.5
AIN2.6
AIN2.7
+
-
+
-
+ 8-to-1
AMUX
-
+
-
Programmable Gain
Amplifier
AV+
X
+
-
8-Bit
SAR
8
ADC
Single-ended or
Differential Measurement
External VREF
Pin
AV+
VREF Start Conversion
Figure 1.13. 8-Bit ADC Diagram
Window
Compare Logic
Window
Compare
Interrupt
ADC Data
Register
Conversion
Complete
Interrupt
Write to AD2BUSY
Timer 3 Overflow
CNVSTR2 Input
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Rev. 1.5
33
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