C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

2. Absolute Maximum Ratings

Table 2.1. Absolute Maximum Ratings*

Parameter

Conditions Min Typ Max Units

Ambient temperature under bias

–55 —

125

°C

Storage Temperature

–65 —

150

°C

Voltage on any Pin (except VDD, Port I/O, and JTAG

pins) with respect to DGND

–0.3 — VDD +

V

0.3

Voltage on any Port I/O Pin, /RST, and JTAG pins with

respect to DGND

–0.3 —

5.8

V

Voltage on VDD with respect to DGND

–0.3 —

4.2

V

Maximum Total current through VDD, AV+, DGND,

and AGND

—

—

800 mA

Maximum output current sunk by any Port pin

—

—

100 mA

Maximum output current sunk by any other I/O pin

—

—

50

mA

Maximum output current sourced by any Port pin

—

—

100 mA

Maximum output current sourced by any other I/O pin

—

—

50

mA

*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the devices at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.



Due to special I/O design requirements of the High Voltage Difference Amplifier, undue electrical over-voltage

stress (i.e., ESD) experienced by these pads may result in impedance degradation of these inputs (HVAIN+

and HVAIN–). For this reason, care should be taken to ensure proper handling and use as typically required to

prevent ESD damage to electrostatically sensitive CMOS devices (e.g., static-free workstations, use of

grounding straps, over-voltage protection in end-applications, etc.)

Rev. 1.5

35

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