C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

1.10. Comparators and DACs

Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on

chip. The MCU data and control interface to each comparator and DAC is via the Special Function Regis-

ters. The MCU can place any DAC or comparator in low power shutdown mode.

The comparators have software programmable hysteresis and response time. Each comparator can gen-

erate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the

MCU from sleep mode. The comparators' output state can also be polled in software. The comparator out-

puts can be programmed to appear on the Port I/O pins via the Crossbar.

The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling

mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The

DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the

internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the

comparators or offsets for the differential inputs of the ADC.

(Port I/O)

CPn Output

CROSSBAR

Comparator inputs

Port 2.[7:2]

CPn+

CPn-

3 Comparators

+

CPn

-

DAC0

(C8051F040/1/2/3 only)

VREF

DAC0

SFR's

(Data

and

C n trl)

VREF

DAC1

(C8051F040/1/2/3 only)

DAC1

Figure 1.14. Comparator and DAC Diagram

C IP -5 1

and

Interrupt

Handler

34

Rev. 1.5

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