C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

4. Pinout and Package Definitions

Name

VDD

DGND

AV+

AGND

TMS

TCK

TDI

TDO

/RST

XTAL1

XTAL2

MONEN

VREF

VREFA

VREF0

VREF2

VREF

AIN0.0

Table 4.1. Pin Definitions

Pin Numbers

Type Description

F040/2/4/6 F041/3/5/7

37, 64, 90 24, 41, 57

Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.

38, 63, 89 25, 40, 56

Digital Ground. Must be tied to Ground.

8, 11, 14

3, 6

Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.

9, 10, 13

4, 5

Analog Ground. Must be tied to Ground.

1

58

D In JTAG Test Mode Select with internal pullup.

2

59

D In JTAG Test Clock with internal pullup.

3

60

D In JTAG Test Data Input with internal pullup. TDI is latched

on the rising edge of TCK.

4

61

D Out JTAG Test Data Output with internal pullup. Data is

shifted out on TDO on the falling edge of TCK. TDO out-

put is a tri-state driver.

5

62

D I/O Device Reset. Open-drain output of internal VDD monitor.

Is driven low when VDD is < 2.7 V and MONEN is high. An

external source can initiate a system reset by driving this

pin low.

26

17

A In Crystal Input. This pin is the return for the internal oscilla-

tor circuit for a crystal or ceramic resonator. For a preci-

sion internal clock, connect a crystal or ceramic resonator

from XTAL1 to XTAL2. If overdriven by an external CMOS

clock, this becomes the system clock.

27

18

A Out Crystal Output. This pin is the excitation driver for a crystal

or ceramic resonator.

28

19

D In VDD Monitor Enable. When tied high, this pin enables the

internal VDD monitor, which forces a system reset when

VDD is < 2.7 V. When tied low, the internal VDD monitor is

disabled.

In most applications, MONEN should be connected

directly to VDD.

12

7

A I/O Bandgap Voltage Reference Output (all devices).

DAC Voltage Reference Input (C8051F041/3 only).

8

A In ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only) 

Voltage Reference Input.

16

A In ADC0 Voltage Reference Input.

17

A In ADC2 Voltage Reference Input (C8051F040/2 only).

15

A In DAC Voltage Reference Input (C8051F040/2 only).

18

9

A In ADC0 Input Channel 0 (See ADC0 Specification for com-

plete description).

Rev. 1.5

37

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