LTC3775 查看數據表（PDF） - Linear Technology

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LTC3775

High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller

Linear Technology 

LTC3775

APPLICATIONS INFORMATION

PULSE-SKIPPING MODE

FORCED CONTINUOUS

0A

0A

DECREASING

LOAD

CURRENT

0A

0A

0A

0A

3775 F09

Figure 9. Comparison of Inductor Current Waveforms for Pulse-Skipping Mode and Forced Continuous Mode

response at low load currents, constant frequency opera-

tion, and the ability to maintain regulation when sinking

current. See Figure 8 for a comparison of the efficiency

at light loads for each mode.

In pulse-skipping mode, the LTC3775 reverse-current

comparator, IREV, monitors the SW pin for zero crossing

when the bottom gate, BG, is high. It turns off BG if the

inductor current reverses and the SW voltage goes above

GND. To prevent false tripping due to ringing on the SW

node when BG is first turned on, there is a blanking time

of 200ns similar to the bottom side current limit blanking.

Under certain light load conditions, if the TG on-time is

short, the inductor current may reverse during the IREV

blanking time but the LTC3775 will only turn off BG after

the blanking time.

In applications where a low value inductor is used, the

high di/dt of the inductor ripple current together with the

parasitic series inductance of the bottom MOSFET, QB,

and PCB trace inductance creates an opposing voltage to

the voltage drop across the RDS(ON) of QB. This can cause

IREV to trip early, before the inductor current reverses.

The parasitic series inductance of the PCB trace can be

minimized by connecting the SW pin closer to the drain

of QB.

INTVCC Regulator

The LTC3775 features a P-channel low dropout linear

regulator (LDO) that supplies power to the INTVCC pin from

the VIN supply. INTVCC powers the gate drivers and much

16

of the LTC3775’s internal circuitry. The LDO regulates the

voltage at the INTVCC pin to 5.2V when VIN is greater than

6.5V. The INTVCC pin must be bypassed to ground with a

low ESR (X5R or better) ceramic capacitor of at least 4.7μF.

Good bypassing is needed to supply the high transient

currents required by the MOSFET gate drivers.

An internal undervoltage lockout (UVLO) monitors the volt-

age on INTVCC to ensure that the LTC3775 has sufficient gate

drive voltage. If the INTVCC voltage falls below the UVLO

threshold of 3.1V, the gate drive outputs remain low.

Thermal Considerations

The LTC3775 is offered in a 3mm × 3mm QFN package

(UD16) that has a thermal resistance RTH(JA) of 68°C/W

and the MSOP (MSE16) package has a thermal resistance

of 40°C/W. Both packages have a lead pitch of 0.5mm.

The regulator can supply up to 50mA of gate drive load cur-

rent. The expected LDO load current can be calculated from

the gate charge requirement of the external MOSFET:

IINTVCC = (fSW) • (QG(QT) + QG(QB)) + 3.5mA

where:

3.5mA is the quiescent current of LTC3775

QG(QT) is the total gate charge of the top MOSFET

QG(QB) is the total gate charge of the bottom MOSFET

fSW is the switching frequency

3775fa

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