LTC3775 查看數據表（PDF） - Linear Technology

零件编号

产品描述 (功能)

生产厂家

LTC3775

High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller

Linear Technology 

LTC3775

APPLICATIONS INFORMATION

INTVCC when the switch node is low. When the top MOSFET

turns on, the switch node rises to VIN and the BOOST pin

rises to approximately VIN + INTVCC. The boost capacitor

needs to store at least 100 times the gate charge required

by the top MOSFET. In most applications a 0.1μF to 1μF

X5R or X7R dielectric capacitor is adequate. The reverse

breakdown of the Schottky diode, DB, must be greater

than VIN(MAX).

Power MOSFET Selection

The LTC3775 requires two external N-channel power

MOSFETs, one for the top (main) switch and one for the

bottom (synchronous) switch. Important parameters for

the power MOSFETs are the threshold voltage V(GS)TH,

breakdown voltage V(BR)DSS, maximum current IDS(MAX),

on-resistance RDS(ON) and input capacitance.

The gate drive voltage is set by the 5.2V INTVCC supply.

Consequently, logic-level threshold MOSFETs must be

used in LTC3775 applications. If the INTVCC voltage is

expected to drop below 5V, then sub-logic level threshold

MOSFETs should be considered. Pay close attention to the

V(BR)DSS specification because most logic-level MOSFETs

are limited to 30V or less. The MOSFETs selected should

have a V(BR)DSS rating greater than the maximum input

voltage and some margin should be added for transients

and spikes.

MOSFET input capacitance is a combination of several

components but can be taken from the typical “gate charge”

curve included on most data sheets (Figure 15). The curve

is generated by forcing a constant input current into the

gate of a common source, current source loaded stage

and then plotting the gate voltage versus time. The initial

slope is the effect of the gate-to-source and the gate-

to-drain capacitance. The flat portion of the curve is the

result of the Miller multiplication effect of the drain-to-gate

VIN

MILLER EFFECT

VGS

V

a

b

QIN

CMILLER = (QB – QA)/VDS

+

+

VGS

VDS

–

–

3775 F15

Figure 15. Gate Charge Characteristics

20

capacitance as the drain voltage drops. The upper sloping

line is due to the drain-to-gate accumulation capacitance

and the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

while the curve is flat) is specified for a given VDS drain

voltage, but can be adjusted for different VDS voltages by

multiplying by the ratio of the application VDS to the curve

specified VDS values. To estimate the capacitance CMILLER,

take the change in gate charge from points a and b on a

manufacturer’s data sheet and divide by the stated VDS

voltage specified. CMILLER is the most important selec-

tion criteria for determining the transition loss term in

the top MOSFET but is not directly specified on MOSFET

data sheets. CRSS and COS are specified sometimes but

definitions of these parameters are not included.

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given

by:

Top Gate Duty Cycle = VOUT

VIN

Bottom

Gate

Duty

Cycle

=





VIN

– VOUT

VIN







The power dissipation for the top and bottom MOSFETs

at maximum output current are given by:

( )( )( ) PTOP

=

VOUT

VIN

IOUT(MAX)2

T(TOP) RDS(ON)(MAX)

( )( ) +VIN2

IOUT(MAX)

2

RDR

CMILLER •

1

+1

INTVCC – VTH(IL) VTH(IL)

• fSW

( ) ( ) ( ) PBOT

=

VIN

– VOUT

VIN

IOUT(MAX)2

T(TOP) RDS(ON)(MAX)

where:

RDR = Effective top driver resistance

VTH(IL) = MOSFET data sheet specified typical gate

threshold voltage at the specified drain current

3775fa

Share Link: