ST72324J6TC 查看數據表（PDF） - STMicroelectronics

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ST72324J6TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro-

grammable versions (FLASH) as well as in factory

coded versions (ROM/FASTROM).

ST72324 devices are ROM versions. ST72P324

devices are Factory Advanced Service Technique

ROM (FASTROM) versions: they are factory-pro-

grammed HDFlash devices. FLASH devices are

shipped to customers with a default content (FFh),

while ROM/FASTROM factory coded parts contain

the code supplied by the customer. This implies

that FLASH devices have to be configured by the

customer using the Option Bytes while the ROM/

FASTROM devices are factory-configured.

14.1 FLASH OPTION BYTES

STATIC OPTION BYTE 0

7

WDG

VD

07

STATIC OPTION BYTE 1

0

OSCTYPE

OSCRANGE

10

10

2

1

0

Default 1 1 1 0 0 1 1 1 1

1

10

1

1

1

1

The option bytes allows the hardware configura-

tion of the microcontroller to be selected. They

have no address in the memory map and can be

accessed only in programming mode (for example

using a standard ST7 programming tool). The de-

fault content of the FLASH is fixed to FFh. To pro-

gram directly the FLASH devices using ICP,

FLASH devices are shipped to customers with the

internal RC clock source. In masked ROM devic-

es, the option bytes are fixed in hardware by the

ROM code (see option list).

OPTION BYTE 0

OPT7= WDG HALT Watchdog and HALT mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = CSS Clock security system on/off

This option bit enables or disables the clock secu-

rity system function (CSS) which includes the

clock filter and the backup safe oscillator.

0: CSS enabled

1: CSS disabled

Caution: The CSS function is not guaranteed. Re-

fer to Section 15.

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection

block (LVD, and AVD) with a selected threshold for

the LVD and AVD (EVD+AVD).

Selected Low Voltage Detector

VD1 VD0

LVD and AVD Off

1

1

Lowest Threshold: (VDD~3V)

Med. Threshold (VDD~3.5V)

Highest Threshold (VDD~4V)

1

0

0

1

0

0

Caution: If the medium or low thresholds are se-

lected, the detection may occur outside the speci-

fied operating voltage range. Below 3.8V, device

operation is not guaranteed. For details on the

AVD and LVD threshold levels refer to Section

12.3.3 on page 117

OPT2:1 = Reserved, must be kept at default value.

OPT0= FMP_R Flash memory read-out protection

This option indicates if the user flash memory is

protected against read-out piracy. This protection

is based on read and a write protection of the

memory in test modes and ICP mode. Erasing the

option bytes when the FMP_R option is selected

causes the whole user memory to be erased first,

and the device can be reprogrammed. Refer to

Section 4.3.1 and the ST7 Flash Programming

Reference Manual for more details.

0: Read-out protection enabled

1: Read-out protection disabled

149/161

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