ST72324J6TC 查看數據表（PDF） - STMicroelectronics
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ST72324J6TC
STMicroelectronics
ST72324J6TC Datasheet PDF : 161 Pages
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ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
OPT7= PKG1 Pin package selection bit
This option bit selects the package.
Version
Selected Package
PKG1
J
TQFP44 / SDIP42
1
K
TQFP32 / SDIP32
0
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Typ. Freq. Range
OSCRANGE
2
1
0
LP
1~2MHz
0
0
0
MP
2~4MHz
0
0
1
MS
4~8MHz
0
1
0
HS
8~16MHz
0
1
1
OPT0 = PLLOFF PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequen-
cy between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
Clock Source
OSCTYPE
1
0
Resonator Oscillator
0
0
Reserved
0
1
Internal RC Oscillator
1
0
External Source
1
1
OPT3:1 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
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