ST6246 查看數據表（PDF） - STMicroelectronics
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ST6246 Datasheet PDF : 72 Pages
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ST62T46B/E46B
LCD CONTROLLER-DRIVER (Continued)
Figure 28. Typical Network to connect to VLCD
pins if VLCD ≤ 4.5V
VLCD
VLCD2/3
VLCD1/3
VSS
R
R
C
R
C
R: 100kΩ
C: 47nF
VR01840
Figure 29. Addressing Map of the LCD RAM
Typical External resistances values are in the
range of 100 KΩ to 150 KΩ. External capacitances
in the range of 10 to 47 nF can be added to VLCD
2/3 and VLCD 1/3 pins and to VLCD if the VLCD con-
nection is highly impedant.
4.5.3 LCD RAM
LCD RAM is organised as a LCD panel with a ma-
trix architecture. Each bit of its content is logically
mapped to a physical element of the display panel
addressed by a couple (Segment;Common). If a
bit is set, the relevant element of the LCD matrix is
turned-on. On the contrary, an element remains
turned-off as long the associated bit within the
LCD RAM is kept cleared.
After a reset, the LCD RAM is not initialised and
contain arbitrary information.
If the choosen multiplexing ratio does not use
some common plates, corresponding RAM ad-
dresses are free for general purpose data storage.
RAM Address MSB
LSB
E0
S8
S7
S6
S5
S4
NA
NA
NA
E1
S16
S15
S14
S13
S12
S11
S10
S9
E2
S24
S23
S22
S21
S20
S19
S18
S17
E3
S32
S31
S30
S29
S28
S27
S26
S25
E4
S40
S39
S38
S37
S36
S35
S34
S33
E5
S48
S47
S46
S45
S44
S43
S42
S41
E6
S8
S7
S6
S5
S4
NA
NA
NA
E7
S16
S15
S14
S13
S12
S11
S10
S9
E8
S24
S23
S22
S21
S20
S19
S18
S17
E9
S32
S31
S30
S29
S28
S27
S26
S25
EA
S40
S39
S38
S37
S36
S35
S34
S33
EB
S48
S47
S46
S45
S44
S43
S42
S41
EC
S8
S7
S6
S5
S4
NA
NA
NA
ED
S16
S15
S14
S13
S12
S11
S10
S9
EE
S24
S23
S22
S21
S20
S19
S18
S17
EF
S32
S31
S30
S29
S28
S27
S26
S25
F0
S40
S39
S38
S37
S36
S35
S34
S33
F1
S48
S47
S46
S45
S44
S43
S42
S41
F2
S8
S7
S6
S5
S4
NA
NA
NA
F3
S16
S15
S14
S13
S12
S11
S10
S9
F4
S24
S23
S22
S21
S20
S19
S18
S17
F5
S32
S31
S30
S29
S28
S27
S26
S25
F6
S40
S39
S38
S37
S36
S35
S34
S33
F7
S48
S47
S46
S45
S44
S43
S42
S41
COM1
COM2
COM3
COM4
50/72
386
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