ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
| |||
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
NAND Flash Controller Interface Timing
Table 33 and Figure 12 on Page 41 through Figure 16 on
Page 43 describe NAND Flash Controller Interface operations.
Table 33. NAND Flash Controller Interface Timing
Parameter
Min
Write Cycle
Switching Characteristics
tCWL
tCH
tCLEWL
tCLH
tALEWL
tALH
tWP1
tWHWL
tWC1
tDWS1
tDWH
Read Cycle
ND_CE Setup Time to AWE Low
ND_CE Hold Time From AWE High
ND_CLE Setup Time to AWE Low
ND_CLE Hold Time From AWE high
ND_ALE Setup Time to AWE Low
ND_ALE Hold Time From AWE High
AWE Low to AWE high
AWE High to AWE Low
AWE Low to AWE Low
Data Setup Time for a Write Access
Data Hold Time for a Write Access
1.0 × tSCLK – 4
3.0 × tSCLK – 4
0.0
2.5 × tSCLK – 4
0.0
2.5 × tSCLK – 4
(WR_DLY +1.0) × tSCLK – 4
4.0 × tSCLK – 4
(WR_DLY +5.0) × tSCLK – 4
(WR_DLY +1.5) × tSCLK – 4
2.5 × tSCLK – 4
Switching Characteristics
tCRL
ND_CE Setup Time to ARE Low
tCRH
ND_CE Hold Time From ARE High
tRP1
ARE Low to ARE High
tRHRL
ARE High to ARE Low
tRC1
ARE Low to ARE Low
Timing Requirements
tDRS
Data Setup Time for a Read Transaction
tDRH
Data Hold Time for a Read Transaction
Write Followed by Read
1.0 × tSCLK – 4
3.0 × tSCLK – 4
(RD_DLY +1.0) × tSCLK – 4
4.0 × tSCLK – 4
(RD_DLY +5.0) × tSCLK – 4
8.02
0.0
Switching Characteristics
tWHRL
AWE High to ARE Low
5.0 × tSCLK – 4
1 WR_DLY and RD_DLY are defined in the NFC_CTL register.
2 The only parameter that differs from 1.8V to 2.5/3.3V operation is tDRS, which is 8.0ns at 2.5/3.3V and is 11ns at 1.8V.
tCWL
tCH
ND_CE
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ND_CLE
ND_ALE
tCLEWL
tALEWL
tCLH
tALH
tWP
AWE
ND_D0-D7
tDWS
tDWH
Figure 12. NAND Flash Controller Interface Timing - Command Write Cycle
Rev. PrG | Page 41 of 80 | February 2009
Share Link: 