ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices
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ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
SDRAM Interface Timing
Table 34. SDRAM Interface Timing
ADSP-BF522/524/526 ADSP-BF523/525/527
VDDMEM =
1.8 V
VDDMEM =
2.5/3.3 V
VDDMEM =
1.8 V
VDDMEM =
2.5/3.3 V
Parameter
Min Max Min Max Min Max Min Max Unit
Timing Requirements
tSSDAT
Data Setup Before CLKOUT
tHSDAT
Data Hold After CLKOUT
Switching Characteristics
tSCLK
CLKOUT Period1
tSCLKH
CLKOUT Width High
tSCLKL
tDCAD
tHCAD
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT2
Command, Address, Data Hold After CLKOUT2
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
1.5
1.5
1.5
1.5
ns
0.8
0.8
1.0
0.8
ns
12.5
12.5
10
7.5
ns
2.5
2.5
2.5
2.5
ns
2.5
2.5
2.5
2.5
ns
4.4
4.4
4.0
4.0 ns
1.0
1.0
1.0
1.0
ns
5.0
5.0
5.0
4.0 ns
0.0
0.0
0.0
0.0
ns
1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.
2 Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
CLKOUT
DATA (IN)
DATA (OUT)
COMMAND, ADDRESS
(OUT)
tSSDAT
tSCLK
tSCLKH
tHSDAT
tSCLKL
tENSDAT
tDCAD
tHCAD
tDSDAT
tDCAD
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 17. SDRAM Interface Timing
Rev. PrG | Page 44 of 80 | February 2009
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