ADSP-BF526BBCZ-4AX 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

External DMA Request Timing

Table 35 and Figure 18 describe the External DMA Request

operations.

Table 35. External DMA Request Timing

Parameter

VDDEXT/VDDMEM = 1.8 V1

Min

Max

VDDEXT/VDDMEM = 2.5/3.3 V

Min

Max Unit

Timing Parameters

tDR

tDH

tDMARACT

tDMARINACT

DMARx Asserted to CLKOUT High Setup

CLKOUT High to DMARx Deasserted Hold Time

DMARx Active Pulse Width

DMARx Inactive Pulse Width

8.0

0.0

1.0 × tSCLK

1.75 × tSCLK

6.0

ns

0.0

ns

1.0 × tSCLK

ns

1.75 × tSCLK

ns

1 Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and

VDDMEM are NOT equal may require level shifting logic for correct operation.

CLKOUT

DMAR0/1

(Active Low)

tDR

tDMARACT

tDH

tDMARINACT

DMAR0/1

(Active High)

tDMARACT

tDMARINACT

Figure 18. External DMA Request Timing

Rev. PrG | Page 45 of 80 | February 2009

Share Link: