CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

11.4 Simple 8-MHz I/O

The Simple I/O type of access is 16-bit only and has a selection of 4 different cycle speeds selectable by

bits 20 and 19 of the address. This type of I/O is selected for addresses in the range 0x3210000 to

0x32FFFFFF. When writing, the upper halfword of the CL-PS7500FE data bus is written out on the I/O

bus. When reading, the I/O bus data is read back onto the lower halfword of the CL-PS7500FE data bus.

This type of I/O cycle is not affected by the READY signal.

During these accesses, the signal nSIOCS1 is always asserted with a read or write strobe as appropriate

based on the CLK8, 8-MHz clock. nSIOCS2 is asserted according to the decoding in the section above.

The read and write strobes are the nIOR and nIOW output pins respectively. The four timings of the Simple

8-MHz I/O accesses are shown below:

Table 11-2. Timings of the Simple 8-MHz I/O accesses

Address [20:19] Name

00

Slow

01

Medium

10

Fast

11

Sync

MIN CLK8 Cycles

7

6

5

5

The ‘sync’ timing is referenced to the 2-MHz CLK2 output, and there is an additional possible synchroni-

zation penalty of up to three CLK8 cycles, depending on the phase of CLK2 and CLK8 at the commence-

ment of the I/O cycle. This is in addition to synchronization between the I/O and memory subsystem

signals.

11.5 Module I/O

The Module I/O type of access is 16-bit only and its speed is controlled by a handshake mechanism with

the external hardware. The signals nIORQ (output) and nIOGT (input) are used for this handshaking.

When writing, the upper half-word of the CL-PS7500FE data bus is written out on the I/O bus. When read-

ing, the I/O bus data is read back onto the lower half-word of the CL-PS7500FE data bus. The module

type of I/O is initiated for addresses in the ranges 0x03000000 to 0x0300FFFF and 0x03030000 to

0x0303FFFF.

During these accesses, the signal nMSCS is asserted but read and write strobes are not used, although

the IORNW signal is active. READY does not affect this type of access.

The nBLI is driven by the external hardware to indicate when the read or write data should be latched from

the BD I/O bus.

The I/O cycle terminates when both nIORQ and nIOGT are low at the rising edge of REF8M.

11.6 PC Bus-Style I/O

This type of I/O is designed to function in conjunction with a standard PC Combo chip, and cycles are

generated from a 16-MHz clock.

The PC bus-style I/O type of access routes the lower halfword of the CL-PS7500FE bus through the

device providing a direct 16-bit interface. Additionally, signals are generated to support the addition of

June 1997

ADVANCE DATA BOOK v2.0

I/O SUBSYSTEMS

111

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