CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Address 0x032000E0 — Interrupt Control

76543210

SFAC4 3 2 1

1

2

3

4

C

A

F

S

Write

channel 1 interrupt enable

channel 2 interrupt enable

channel 3 interrupt enable

channel 4 interrupt enable

any combination of channels generates nIRQ

only all channels enabled generates nIRQ

first pair enabled generates nIRQ

second pair enabled generates nIRQ

bit[7:0]

0

disabled

1

enabled

Read

Reset

return above values

reset to 0x0F

NOTE: The OR of bit[3:0] powers up all the comparators. Thus they reset to the powered-up state.

11.10.3 Status of Interface

The status of the ‘stop’ flag for each channel can be read directly from bits 0–3 of the status register, as

can the interrupt status that is the logical AND of the ‘stop’ flag values and the corresponding channel

enables from the interrupt control register.

This register should be read by the system software in a polled system to check whether a channel has

reached its final count value and is thus waiting to be read before another conversion cycle can be initi-

ated.

Address 0x032000E4 — Status

76543210

RRRRSSSS

R[3:0]

S[3:0]

Write

Read

Reset

interrupt request state for channels 4 to 1

stop flag for channels 4 to 1

ignored

bit[7:4]

0

not requesting

1

requesting

set all zero (not requesting)

June 1997

ADVANCE DATA BOOK v2.0

I/O SUBSYSTEMS

117

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