CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

76543210

X X X XCCNN

C

N

Write

Read

Reset

nCCS + pseudo DMA access speed

nPCCS1 and nPCCS2 area access speed

bits[7:6] unused

bits[5:4] unused

bits[3:2]

00 Type A (slowest)

01 Type B

10 Type C

11 Type D (fastest)

bits[1:0]

00 Type A (slowest)

01 Type B

10 Type C

11 Type D (fastest)

read back above values

set to ‘0’ (slowest)

The extended address space from address 0x08000000 up for 16-MHz I/O accesses supports only cycle

types A and C, and the ECTCR register should be programmed to specify the cycle type required for each

of the eight 16-Mbyte areas within the extended address space. The details of this register, at address

0x032000C8, are shown below:

76543210

EEEEEEEE

E = expansion card area access speed

Write

bit[7] (0F00 0000..0FFF FFFF)

0

Type A

1

Type C

bit[0] (0800 0000..08FF FFFF)

0

Type A

1

Type C

Read

read back above values

Reset

set to ‘0’ (slowest)

This type of I/O asserts a single chip select according to the area, except in Combo DACK + TC space,

where both the nCDACK and TC outputs are asserted to signal to the PC Combo chip that the end of a

pseudo DMA sequence has been reached. In the extended address space the nEASCS chip select is

asserted.

June 1997

ADVANCE DATA BOOK v2.0

I/O SUBSYSTEMS

113

Share Link: