CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

11.7 DMA During I/O Cycles

DMA to the Video and Sound Macrocell can continue during I/O cycles. Write data from the ARM proces-

sor is latched early, so that the data bus can be used freely for DMA data. Thus, only the start of an I/O

cycle needs to be added to any DMA latency calculations.

11.8 Clock Synchronization Conditions

76543210

AXXXXXXX

In a system using a MEMCLK frequency greater than I_OCLK, it may be necessary to insert an extra I/O

clock cycle to allow sufficient address hold time before the chip select is taken away. The problem arises

because the chip select is generated from the fixed frequency I/O world clock, whereas the address

changes according to the memory system clock. When a faster MEMCLK is used, it is possible for

the synchronization to the memory clock to occur rapidly at the end of the cycle, and thus for the I/O

address to change before the chip select has been removed. This may be a problem for some peripherals.

To avoid this, there is a register bit in the ASTCR register (address 0x032000CC) that is normally set to

‘0’, but can be programmed to ‘1’ to add an extra I/O clock period, ensuring that the address does not

change before the chip select is deasserted.

A

asynchronous timing control

0

minimal delay

1

wait states to ensure address hold time

See Appendix C for more information on the use of this register with high MEMCLK frequencies.

11.9

Keyboard/mouse Interface

76543210

T TRREPDC

The keyboard and mouse interfaces are identical, differing only in the names of the external pins. The

interfaces are designed to communicate with a standard PS/2 keyboard or mouse, through a 2 pin serial

link.

The keyboard interface uses the pins KBDATA, KBCLK, and the mouse interface uses the pins MSDATA

and MSCLK, all are open-drain.

There is an 8-bit control register for each interface, providing direct access to the CLK and DATA outputs,

an enable bit to enable the interface, and five status flags. The KBDCR is programmed at address

0x03200008, and the MSECR (mouse control register) at address 0x032000AC.

T

transmit status

R

receive status

E

enable

P

received parity

D

data pin status

C

clock pin status

114

I/O SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

Share Link: