CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

19.6 Instruction Cycle Timing

The following table shows the number of cycles that FPA takes in executing each instruction. Two numbers

are given:

q The instruction latency

q The maximum instruction throughput

Table 19-8. FPA Cycle Time

Instruction

Precision

LDF/STF

LDF/STF

LDF/STF

LFM/SFM

LFM/SFM

LFM/SFM

LFM/SFM

MVF/MNF/ABS

ADF/SUF/RSF/URD/NRM

MUF

FML

DVF/RDF/FDV/FRD

DVF/RDF/FDV/FRD

DVF/RDF/FDV/FRD

FLT

FIX

CMF/CMFE/CNF/CNFE

RFS/RFC

WFS/WFC

S

D

E

S/D/E

S/D/E

S/D/E

S/D/E

S

D

E

S/D/E

No. Regis-

ters

1

2

3

4

Throughput Latency

2

3

3

4

4

5

4

5

7

8

10

11

13

14

1

2

2

4

8

9

5

6

30

31

58

59

70

71

6

8

8

9

5

6

3

4

3

3

Note

1

2

2

2

3

NOTES:

1) Cannot be sustained for more than 2 cycles out of every 3 cycles.

2) May be less if the division comes out exactly, causing early termination of the division algorithm (minimum of 6

cycles throughput, 7 cycles latency).

3) May be 2 or 3 cycles, depending on the previous instruction.

June 1997

ADVANCE DATA BOOK v2.0

FLOATING-POINT INSTRUCTION SET

183

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