CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

External buffered and unbuffered write cycles occur with indistinguishable bus timing. When the ARM

needs to read from a location and the data is not in the cache or is uncacheable (for example, for I/O), an

external read access is performed.

20.3 Video DMA Bandwidth

The maximum video DMA bandwidth depends on the MEMCLK frequency and the DRAM width (16 or

32 bit), but can be calculated as follows. The length of the non-sequential cycle at the start of a DRAM

read varies. Assuming DRAMCR[5] is low:

q In Page mode, each non-sequential cycle takes 5 cycles

q In EDO mode, each non-sequential cycle takes 6 cycles

This increases by one if DRAMCR[5] is high, and again by one or two to preserve RAS precharge times,

depending on whether the access just finished was to the same bank as the current one and if

DRAMCR[6] is also set.

Assuming Fast Page mode without further non-sequential delays, each qword DMA requires 5 + 2 + 2 +

2 = 11 MEMCLK cycles to complete. It is possible for DMA requests for the video to be serviced sequen-

tially such that the second and subsequent qword DMA bursts take only 2 + 2 + 2 + 2 = 8 MEMCLK

cycles each. However, all accesses is broken up at page boundaries (every 256 words). So every 64 DMA

bursts, three extra MEMCLK periods are required.

Therefore, at a 32 MHz MEMCLK with a 32-bit-wide DRAM, 64 qwords would be transferred approxi-

mately every 16 µs. The maximum theoretical DMA bandwidth is thus 63.6 Mbytes/sec. If a greater video

DMA bandwidth is required, a higher MEMCLK frequency must be used. In an actual system, the average

bandwidth does not achieve this theoretical maximum.

20.4 Video DMA Latency

DMA latency is defined as the time from the generation of the internal request for more data from the video

FIFO in the video macrocell, to the time that the first word of DMA data is clocked into the video macrocell.

There are several possible limiting factors that can determine the worst-case DMA latency. This depends

on the CL-PS7500FE memory system configuration. There are three possible limiting cases:

1) Internal register programming cycles.

2) Burst mode ROM accesses, or very long non-sequential ROM accesses.

3) DRAM accesses in 16-bit mode.

The following assumes that the internal MEMRFCK frequency is equal to the MEMCLK frequency (that

is, the prescalars are set to divide-by-one). The above cases determine the maximum period before arbi-

tration for DMA occurs in different systems. In addition to the latency resulting from these sequences, the

worst-case DMA latency has a possible 5.5 MEMCLK cycles factor for synchronization, such that the syn-

chronized request arrives just too late to be arbitrated for, and CL-PS7500FE commits to a memory cycle.

The 5.5 MEMCLK cycles also includes the ARM processor idle cycle where the arbitration (that was just

missed) occurs.

From the clock edge where arbitration finally occurs, to the time the first word of DMA data is clocked into

the video macrocell, is 5.5 MEMCLK cycles or 7.5 MEMCLK cycles if the preceding access was to DRAM

in the same bank. These values assume DRAMCR[7:5] are all set high (that is, EDO memory).

188

BUS INTERFACE

ADVANCE DATA BOOK v2.0

June 1997

Share Link: