DA28F320S5-110 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DA28F320S5-110 Datasheet PDF : 50 Pages
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28F160S5, 28F320S5
E
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read
Status Register
0
SR.7 =
1
Full Status
Check if Desired
Bus
Operation
Command
Comments
Write
Write
Set
Block/Master
Lock-Bit Setup
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Set
Block or Master
Lock-Bit Confirm
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
Voltage Range Error
0
1
SR.1 =
Device Protect Error
0
1
SR.4,5 =
0
Command Sequence
Error
1
SR.4 =
0
Set Lock-Bit Successful
Set Lock-Bit Error
Bus
Operation
Command
Comments
Standby
Standby
Standby
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect Detect
RST# = VIH
(Set Master Lock-Bit Operation)
RST# = VIH, Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
Check SR.4,5
Both 1 = Command Sequence Error
Standby
Check SR.4
1 = Set Lock-Bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set
before full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Figure 11. Set Block Lock-Bit Flowchart
36
ADVANCE INFORMATION
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