DA28F320S5-110 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DA28F320S5-110 Datasheet PDF : 50 Pages
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28F160S5, 28F320S5
E
5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
Intel provides three control inputs to accommodate
multiple memory connections: CEX# (CE0#, CE1#),
OE#, and RP#. Three-line control provides for:
a. Lowest possible memory power dissipation;
b. Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CEx# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs, while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 STS and WSM Polling
STS is an open drain output that should be
connected to VCC by a pull-up resistor to provide a
hardware form of detecting block erase, program,
and lock-bit configuration completion. In default
mode, it transitions low during execution of these
commands and returns to VOH when the WSM has
finished executing the internal algorithm. For
alternate STS pin configurations, see Section 4.10.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also VOH when the device
is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. Standby current
levels, active current levels and transient peaks
produced by falling and rising edges of CEX# and
OE# are areas of interest. Two-line control and
proper decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
VCC and GND and VPP and GND. These high-
frequency, low-inductance capacitors should be
placed as close as possible to package leads.
38
Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between VCC and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
5.4 VPP Trace on Printed Circuit
Boards
Updating target-system resident flash memories
requires that the printed circuit board designer pay
attention to VPP power supply traces. The VPP pin
supplies the memory cell current for programming
and block erasing. Use similar trace widths and
layout considerations given to the VCC power bus.
Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
5.5 VCC, VPP, RP# Transitions
Block erase, program, and lock-bit configuration are
not guaranteed if RP# ≠ VIH, or if VPP or VCC fall
outside of a valid voltage range (VCC1/2 and VPPH).
If VPP error is detected, Status Register bit SR.3
and SR.4 or SR.5 are set to “1.” If RP# transitions
to VIL during block erase, program, or lock-bit
configuration, STS in level RY/BY# mode will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. Because the aborted
operation may leave data partially altered, the
command sequence must be repeated after normal
operation is restored.
5.6 Power-Up/Down Protection
The device offers protection against accidental
block erase, programming, or lock-bit configuration
during power transitions.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CEX# must be low for a
command write, driving either input signal to VIH will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. RP# = VIL disables
the device regardless of its control inputs states.
ADVANCE INFORMATION
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