28F160S5, 28F320S5
E
6.2.1
CAPACITANCE
Table 18. Capacitance(1), TA = +25°C, f = 1 MHz
Symbol
Parameter
Typ
Max
Unit
CIN
Input Capacitance
6
8
pF
COUT
Output Capacitance
NOTE:
1. Sampled, not 100% tested.
8
12
pF
Condition
VIN = 0.0V
VOUT = 0.0V
6.2.2
AC INPUT/OUTPUT TEST CONDITIONS
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 5.0V ± 5%
(High Speed Testing Configuration)
2.4
2.0
INPUT
TEST POINTS
2.0
OUTPUT
0.8
0.8
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 5.0V ± 10%
(Standard Testing Configuration)
1.3V
1N914
DEVICE
UNDER
TEST
C L Includes Jig
Capacitance
R L = 3.3 kΩ
OUT
CL
Figure 15. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
CL (pF)
VCC = 5.0V ± 5%
30
VCC = 5.0V ± 10%
100
40
ADVANCE INFORMATION