ADP3208CJCPZ-RL View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
ADP3208CJCPZ-RL
ON Semiconductor
ADP3208CJCPZ-RL Datasheet PDF : 41 Pages
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ADP3208C
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is greater
than CX(MAX), the system does not meet the VID on-the-fly
and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.
For example, if 30 pieces of 10 μF, 0805-size MLC capacitors
(CZ = 300 μF) are used, the fastest VID voltage change is when
the device exits deeper sleep, during which the VCORE change is
220 mV in 22 μs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields
⎜⎛
⎟⎞
C
X ( MIN )
≥
⎜
⎜
⎜
⎜⎜⎝
2
×
⎜⎛
⎜⎝
2.1
330 nH × 27.9 A
mΩ+
10 mV
27.9 A
⎟⎞
⎟⎠
×
1.4375
V
−
300
⎟
μF ⎟
⎟
⎟⎟⎠
=
1.0
mF
330 nH × 220 mV
C X(MAX ) ≤ 2 × 3.12 × (2.1 mΩ)2 × 1.4375 V ×
⎜⎛
⎜
⎜⎝
1
+
⎜⎜⎝⎛
22
μs
×
1.4375 V
220 mV
×
×
2 × 3.1 ×
490 nH
2.1
mΩ
⎟⎟⎠⎞
2
⎟⎞
−1⎟ − 300 μF
⎟⎠
= 21 mF
Using six 330 μF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 1.98 mF and RX = 1.2 mΩ.
Ensure that the ESL of the bulk capacitors (LX) is low enough to
limit the high frequency ringing during a load change. This is
tested using
LX ≤ CZ × RO2×Q2
(12)
( ) LX ≤ 300 μF × 2.1 mΩ 2 ×2 = 2 nH
where:
Q is limited to the square root of 2 to ensure a critically damped
system.
LX is about 150 pH for the six SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of the
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 10, 11, and 12
are satisfied.
Power MOSFETs
For typical 20 A per phase applications, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection
parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS,
and RDS(ON). Because the voltage of the gate driver is 5 V, logic-
level threshold MOSFETs must be used.
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3208C, currents are balanced between phases; the current
in each low-side MOSFET is the output current divided by the
total number of MOSFETs (nSF). With conduction losses being
dominant, the following expression shows the total power that
is dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and the average total output
current (IO):
PSF
=
(1
−
D)
×
⎢⎢⎣⎡⎜⎜⎝⎛
IO
nSF
⎟⎟⎠⎞2
+
1
12
×
⎜⎜⎝⎛
n×I
nSF
R
⎟⎟⎠⎞
2
⎤
⎥
⎥⎦
×
R
DS(SF
)
(13)
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak-to-peak ripple current and is
approximately
IR
=
(1 − D)×VOUT
L × f SW
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOIC-
compatible MOSFETs, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and
a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction tem-
perature. Therefore, for this example (40 A maximum), the RDS(SF)
per MOSFET is less than 8.5 mΩ for two pieces of low-side
MOSFETs. This RDS(SF) is also at a junction temperature of about
120°C; therefore, the RDS(SF) per MOSFET should be less than
6 mΩ at room temperature, or 8.5 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
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