ADP3208CJCPZ-RL View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
ADP3208CJCPZ-RL
ON Semiconductor
ADP3208CJCPZ-RL Datasheet PDF : 41 Pages
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ADP3208C
PS( MF )
= 2×
f SW
× VDC × IO
nMF
× RG
×
nMF
n
× CISS
(14)
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance.
CISS is the input capacitance of the main MOSFET.
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
PC(MF )
=
D
×
⎢⎢⎣⎡⎜⎜⎝⎛
IO
n MF
⎟⎟⎠⎞2
+
1
12
×
⎜⎜⎝⎛
n×IR
n MF
⎟⎟⎠⎞
2
⎤
⎥
⎥⎦
×
R
DS(
MF
)
(15)
where RDS(MF) is the on resistance of the MOSFET.
Typically, a user wants the highest speed (low CISS) device
for a main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (about 0.8 W to 1.0 W for an 8-lead
SOIC) when combining the switching and conduction losses.
For example, an IRF7821 device can be selected as the main
MOSFET (four in total; that is, nMF = 4), with approximately
CISS = 1010 pF (maximum) and RDS(MF) = 18 mΩ (maximum at
TJ = 120°C), and an IR7832 device can be selected as the
synchronous MOSFET (four in total; that is, nSF = 4), with
RDS(SF) = 6.7 mΩ (maximum at TJ = 120°C). Solving for the
power dissipation per MOSFET at IO = 40 A and IR = 9.0 A
yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
( ) PDRV
=
⎡
⎢⎣
f
2
SW
×n
×
n MF
× QGMF
+ nSF
× QGSF
+
I
CC
⎤
⎥⎦
×
VCC
(16)
where QGMF is the total gate charge for each main MOSFET, and
QGSF is the total gate charge for each synchronous MOSFET.
The previous equation also shows the standby dissipation
(ICC times the VCC) of the driver.
Ramp Resistor Selection
The ramp resistor (RR) is used to set the size of the internal PWM
ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Use the following expression to determine a starting value:
(17)
RR
=
3×
AR × L
AD × RDS
× CR
RR
=
0.5 × 360 nH
3× 5 × 5.2 mΩ × 5 pF
=
462 kΩ
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low-side MOSFET ON-resistance,
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 18). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of RR in this example is selected as 280 kΩ.
The internal ramp voltage magnitude can be calculated as follows:
VR
=
AR × (1 − D) ×VVID
RR × CR × fSW
(18)
VR
=
0.5 × (1 − 0.061) ×1.150 V
462 kΩ × 5 pF × 280 kHz
=
0.83 V
The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 17, the factor
of 3 sets the minimum ramp size that produces an optimal
combination of good stability, transient response, and thermal
balance.
COMP Pin Ramp
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
VRT
=
⎜⎜⎝⎛1 −
VR
2× (1− n× D)
n× f SW ×C X × RO
⎟⎟⎠⎞
(19)
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator.
For this example, the overall ramp signal is 1.85 V.
Rev. 1 | Page 35 of 41 | www.onsemi.com
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