ADP3208CJCPZ-RL View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

ADP3208CJCPZ-RL

7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller

ON Semiconductor 

5. The resulting waveform will be similar to that shown in

Figure 41. Use the horizontal cursors to measure VACDRP and

VDCDRP, as shown in Figure 41. Do not measure the under-

shoot or overshoot that occurs immediately after the step.

ADP3208C

VDROOP

VACDRP

VDCDRP

Figure 41. AC Load Line Waveform

6. If the difference between VACDRP and VDCDRP is more than a

couple of millivolts, use Equation 46 to adjust CCS. It may

be necessary to try several parallel values to obtain an

adequate one because there are limited standard capacitor

values available (it is a good idea to have locations for two

capacitors in the layout for this reason).

CCS(NEW )

= CCS(OLD)

× VACDRP

VDCDRP

(37)

7. Repeat Steps 5 and 6 until no adjustment of CCS is needed.

Once this is achieved, do not change CCS for the rest of the

procedure.

8. Set the dynamic load step to its maximum step size (but do

not use a step size that is larger than needed) and verify

that the output waveform is square, meaning VACDRP and

VDCDRP are equal.

9. Ensure that the load step slew rate and the power-up slew

rate are set to ~150 A/μs to 250 A/μs (for example, a load

step of 50 A should take 200 ns to 300 ns) with no

overshoot. Some dynamic loads have an excessive

overshoot at power-up if a minimum current is incorrectly

set (this is an issue if a VTT tool is in use).

Set the Initial Transient

1. With the dynamic load set at its maximum step size,

expand the scope time scale to 2 μs/div to 5 μs/div. This

results in a waveform that may have two overshoots and

one minor undershoot before achieving the final desired

value after VDROOP (see Figure 42).

VTRAN1

VTRAN2

Figure 42. Transient Setting Waveform, Load Step

2. If both overshoots are larger than desired, try the following

adjustments in the order shown.

a. Increase the resistance of the ramp resistor

(RRAMP) by 25%.

b. For VTRAN1, increase CB or increase the switching

frequency.

c. For VTRAN2, increase RA by 25% and decrease CA by 25%.

If these adjustments do not change the response, it is

because the system is limited by the output decoupling.

Check the output response and the switching nodes each

time a change is made to ensure that the output decoupling

is stable.

3. For load release (see Figure 43), if VTRANREL is larger than

the value specified by IMVP-6+, a greater percentage of

output capacitance is needed. Either increase the

capacitance directly or decrease the inductor values. (If

inductors are changed, however, it will be necessary to

redesign the circuit using the information from the

spreadsheet and to repeat all tuning guide procedures).

VTRANREL

VDROOP

Figure 43. Transient Setting Waveform, Load Release

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

Rev. 1 | Page 39 of 41 | www.onsemi.com

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