ADP3208CJCPZ-RL View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
ADP3208CJCPZ-RL
ON Semiconductor
ADP3208CJCPZ-RL Datasheet PDF : 41 Pages
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ADP3208C
Current Limit Setpoint
To select the current-limit setpoint, we need to find the resistor
value for RLIM. The current-limit threshold for the ADP3208C is
set when the current in RLIM is equal to the internal reference
current of 20 μA. The current in RLIM is equal to the inductor
current times RO. RLIM can be found using the following
equation:
RLIM
=
ILIM × RO
20μA
(25)
where:
RLIM is the current limit resistor. RLIM is connected from the
ILIM pin to ground.
RO is the output load line resistance.
ILIM is the current limit set point. This is the peak inductor
current that will trip current limit.
to filter the inductor current ripple and high frequency load
transients. Since the IMON pin is connected directly to the
CPU, it is clamped to prevent it from going above 1.15V.
The IMON pin current is equal to the RLIMtimes a fixed gain of
10. RMON can be found using the following equation:
RMON
=
1.15V × RLIM
10× RO × IFS
(28)
where:
RMON is the current monitor resistor. RMON is connected from
IMON pin to FBRTN.
RLIM is the current limit resistor.
RO is the output load line resistance.
IFS is the output current when the voltage on IMON is at full
scale.
In this example, if choosing 55 A for ILIM, RLIM is 5.775 kΩ,
which is close to a standard 1% resistance of 5.76 kΩ.
The per-phase current limit described earlier has its limit
determined by the following:
I PHLIM
≅
VCOMP(MAX) − VR − VBIAS
AD × RDS(MAX)
+
IR
2
(26)
For the ADP3208C, the maximum COMP voltage (VCOMP(MAX))
is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the
current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V,
and a RDS(MAX) of 3.8 mΩ (low-side on-resistance at 150°C)
results in a per-phase limit of 85 A. Although this number
seems high, this current level can only be reached with a
absolute short at the output and the current-limit latch-off
function shutting down the regulator before overheating occurs.
This limit can be adjusted by changing the ramp voltage VR.
However, users should not set the per-phase limit lower than
the average per-phase current (ILIM/n).
There is also a per-phase initial duty-cycle limit at maximum
input voltage:
D LIM
= D MIN
× VCOMP(MAX)
VR
− VBIAS
(27)
Feedback Loop Compensation Design
Optimized compensation of the ADP3208C allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (RO). With the resistive output impedance, the output
voltage droops in proportion with the load current at any load
current slew rate, ensuring the optimal position and allowing
the minimization of the output decoupling.
With the multimode feedback structure of the ADP3208C, it is
necessary to set the feedback compensation so that the
converter’s output impedance works in parallel with the output
decoupling. In addition, it is necessary to compensate for the
several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 37 shows the
Type III amplifier used in the ADP3208C. Figure 38 shows the
locations of the two poles and two zeros created by this amplifier.
For this example, the duty-cycle limit at maximum input
voltage is found to be 0.25 when D is 0.061.
Output Current monitor
The ADP3208C has output current monitor. The IMON pin
sources a current proportional to the total inductor current. A
resistor, RMON, from IMON to FBRTN sets the gain of the
output current monitor. A 0.1 μF is placed in parallel with RMON
Rev. 1 | Page 36 of 41 | www.onsemi.com
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