PIC16LF870-I/SO View Datasheet(PDF) - Microchip Technology
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PIC16LF870-I/SO Datasheet PDF : 156 Pages
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PIC16F870/871
FIGURE 14-13: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK 132
A/D DATA
(TOSC/2)(1)
1 TCY
131
130
9
8
7 ... ...
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
GO
DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
130 TAD A/D clock period
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
131 TCNV Conversion time (not including S/H time)
(Note 1)
132 TACQ Acquisition time
Min
1.6
3.0
2.0
3.0
Note 2
Typ†
—
—
4.0
6.0
—
40
Max Units
Conditions
—
µs TOSC based, VREF ≥ 3.0V
—
µs TOSC based, VREF ≥ 2.0V
6.0
µs A/D RC Mode
9.0
µs A/D RC Mode
12
TAD
—
µs
10*
—
—
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134 TGO Q4 to A/D clock start
— TOSC/2 § —
— If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30569A-page 134
Preliminary
© 1999 Microchip Technology Inc.
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