ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

XVI.4.2 - Definition of internal timing

The internal operation of the ST10F163 is con-

trolled by the internal CPU clock fCPU. Both edges

of the CPU clock can trigger internal (e.g. pipe-

line) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Char-

acteristics) therefore depends on the time

between two consecutive edges of the CPU clock,

called “TCL” (see figure below).

The CPU clock signal can be generated by differ-

ent mechanisms. The duration of TCLs and their

variation (and also the derived external timing)

depends on the used mechanism to generate

fCPU. This influence must be regarded when cal-

culating the timings for the ST10F163.

The example for PLL operation shown in the fig-

ure above refers to a PLL factor of 4. The mecha-

nism used to generate the CPU clock is selected

during reset by the logic levels on pins P0.15-13

(P0H.7-5).

Figure 11 : Generation mechanisms for the CPU clock

Phase locked loop operation

fXTAL

fCPU

Direct Clock Drive

fXTAL

fCPU

Prescaler Operation

fXTAL

fCPU

TCLTCL

TCLTCL

TCL TCL

XVI.4.3 - Clock generation modes

The table below associates the combinations of these three bits with the respective clock generation mode.

P0.15-13

(P0H.7-5)

CPU Frequency

fCPU = fXTAL * F

External Clock Input

Range1)

Notes

111

110

101

100

011

010

001

000

FXTAL * 4

FXTAL * 3

FXTAL * 2

FXTAL * 5

FXTAL * 1

FXTAL * 1.5

FXTAL / 2

FXTAL * 2.5

2.5 to 6.25 MHz

3.33 to 8.33 MHz

5 to 12.5 MHz

2 to 5 MHz

1 to 25 MHz

6.66 to 16.6 MHz

2 to 50 MHz

4 to 10 MHz

Default configuration

Direct drive 2)

CPU clock via prescaler3)

1. The external clock input range refers to a CPU clock range of 1...25 MHz.

2. The maximum depends on the duty cycle of the external clock signal.

3. The maximum input frequency is 25 MHz when using an external crystal with the internal oscillator; providing that internal serial resistance

of the crystal is less than 40 Ω. However, higher frequency can be applied with an external clock source, but in this case, the input clock

signal must reach the defined levels VIL and VIH2.

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