ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

XVI.4.4 - Prescaler operation

When pins P0.15-13 (P0H.7-5) equal ’001’ during

reset, the CPU clock is derived from the internal

oscillator (input clock signal) by a 2:1 prescaler.

The frequency of fCPU is half the frequency of

fXTAL and the high and low time of fCPU (i.e. the

duration of an individual TCL) is defined by the

period of the input clock fXTAL.

The timings listed in the AC Characteristics that

refer to TCLs therefore can be calculated using

the period of fXTAL for any TCL.

Note that if the bit OWDDIS in SYSCON register

is cleared, the PLL is running on its free-running

frequency and delivers the clock signal for the

Oscillator Watchdog. If bit OWDDIS is set, then

the PLL is switched off.

XVI.4.5 - Direct drive

When pins P0.15-13 (P0H.7-5) equal’011’ during

reset the on-chip phase locked loop is disabled

and the CPU clock is directly driven from the inter-

nal oscillator with the input clock signal.

The frequency of fCPU directly follows the fre-

quency of fXTAL so the high and low time of fCPU

(i.e. the duration of an individual TCL) is defined

by the duty cycle of the input clock fXTAL.

The timings listed below that refer to TCLs there-

fore must be calculated using the minimum TCL

that is possible under the respective circum-

stances. This minimum value can be calculated

by the following formula:

T CLmin= 1 ⁄ fXT AL*DCmin

DC= duty cycle

For two consecutive TCLs the deviation caused

by the duty cycle of fXTAL is compensated so the

duration of 2TCL is always 1/fXTAL. The minimum

value TCLmin therefore has to be used only once

for timings that require an odd number of TCLs

(1,3,...). Timings that require an even number of

TCLs (2,4,...) may use the formula:

2TCL= 1 ⁄ fXTAL

Note

The address float timings in Multiplexed bus mode (t11 and

t45) use the maximum duration of TCL (TCLmax = 1/fXTAL *

DCmax) instead of TCLmin.

If bit OWDDIS in the SYSCON register is cleared,

the PLL runs on its free-running frequency and

delivers the clock signal for the Oscillator Watch-

dog. If bit OWDDIS is set, then the PLL is

switched off.

XVI.4.6 - Oscillator Watchdog (OWD)

When the clock option selected is direct drive or

direct drive with prescaler, in order to provide a fail

safe mechanism in case of a loss of the external

clock, an oscillator watchdog is implemented as

an additional functionality of the PLL circuitry. This

oscillator watchdog operates as follows:

After a reset, the Oscillator Watchdog is enabled

by default. To disable the OWD, the bit OWDDIS

(bit 4 of SYSCON register) must be set.

When the OWD is enabled, the PLL is running on

its free-running frequency, and increment the

Oscillator Watchdog counter. On each transition of

XTAL1 pin, the Oscillator Watchdog is cleared. If

an external clock failure occurs, then the Oscillator

Watchdog counter overflows (after 16 PLL clock

cycles). The CPU clock signal will be switched to

the PLL free-running clock signal, and the Oscilla-

tor Watchdog Interrupt Request (XP3INT) is

flagged. The CPU clock will not switch back to the

external clock even if a valid external clock exits

on XTAL1 pin. Only a hardware reset can switch

the CPU clock source back to direct clock input.

When the OWD is disabled, the CPU clock is

always fed from the oscillator input and the PLL is

switched off to decrease power supply current.

XVI.4.7 - Phase locked loop

For all other combinations of pins P0.15-13

(P0H.7-5) during reset the on-chip phase locked

loop is enabled and provides the CPU clock (see

table above). The PLL multiplies the input fre-

quency by the factor F which is selected via the

combination of pins P0.15-13 (i.e. fCPU = fXTAL *

F). With every F’th transition of fXTAL the PLL cir-

cuit synchronizes the CPU clock to the input

clock. This synchronization is done smoothly, i.e.

the CPU clock frequency does not change

abruptly.

Due to this adaptation to the input clock the fre-

quency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter

of fCPU which also effects the duration of individ-

ual TCLs.

The timings listed in the AC Characteristics that

refer to TCLs therefore must be calculated using

the minimum TCL that is possible under the

respective circumstances.

35/58

Share Link: