ST10F163 View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
ST10F163 Datasheet PDF : 58 Pages
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ST10F163
XVI.4.10 - Multiplexed bus
VDD = 5 V ± 10%
VSS = 0 V
TA = 0 to +70°C
CL = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25-MHz CPU clock without waitstates)
Table 16 : Multiplexed bus characteristics
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR (with RW-delay)
ALE falling edge to RD, WR (no RW-delay)
Address float after RD, WR (with RW-delay)
Address float after RD, WR (no RW-delay)
RD, WR low time (with RW-delay)
RD, WR low time (no RW-delay)
RD to valid data in (with RW-delay)
RD to valid data in (no RW-delay)
ALE low to valid data in
Address/Unlatched CS to valid data in
Data hold after RD rising edge
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold after RD, WR
Symbol
Max. CPU Clock
25 MHz
min.
max.
Variable CPU Clock
1/2TCL = 1 to 25MHz
min.
max.
t5 CC
t6 CC
t7 CC
t8 CC
t9 CC
t10 CC
t11 CC
t12 CC
t13 CC
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
t19 SR
t22 CC
t23 CC
t25 CC
t27 CC
10 + tA
4 + tA
10 + tA
10 + tA
-10 + tA
–
–
30 + tC
50 + tC
–
–
–
–
0
–
20 + tC
26 + tF
26 + tF
26 + tF
–
TCL - 10
–
ns
+ tA
–
TCL -
–
ns
16+ tA
–
TCL - 10
–
ns
+ tA
–
TCL - 10
–
ns
+ tA
–
-10 + tA
–
ns
6
–
6
ns
26
–
TCL + 6 ns
–
2TCL - 10
–
ns
+ tC
–
3TCL - 10
–
ns
+ tC
20 + tC
–
2TCL - 20 ns
+ tC
40 + tC
–
3TCL - 20 ns
+ tC
40
+ tA + tC
–
3TCL - 20 ns
+ tA + tC
50 +2tA +
–
4TCL - 30 ns
tC
+ 2tA + tC
–
0
–
ns
26 + tF
–
–
–
–
–
2TCL - 14 ns
+ tF
2TCL - 20
–
ns
+ tC
2TCL - 14
–
ns
+ tF
2TCL - 14
–
ns
+ tF
2TCL - 14
–
ns
+ tF
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