ST10F163 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F163 Datasheet PDF : 58 Pages
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ST10F163
XVI.4.11 - Demultiplexed bus
VDD = 5 V ± 10%
VSS = 0 V
TA = 0 to +70 °C
CL = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Table 17 : Demultiplexed bus characteristics
Parameter
ALE high time
Address setup to ALE
Address/Unlatched CS setup to RD, WR
(with RW-delay)
Address/Unlatched CS setup to RD, WR
(no RW-delay)
RD, WR low time (with RW-delay)
RD, WR low time (no RW-delay)
RD to valid data in (with RW-delay)
RD to valid data in (no RW-delay)
ALE low to valid data in
Address/Unlatched CS to valid data in
Data hold after RD rising edge
Data float after RD rising edge (with RW-delay1))
Data float after RD rising edge (no RW-delay1))
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold after RD, WR 2)
ALE falling edge to Latched CS
Symbol
Max. CPU Clock
= 25MHz
min.
max.
Variable CPU Clock
1/2TCL = 1 to 25MHz
min.
max.
t5 CC
t6 CC
t80 CC
t81 CC
t12 CC
t13 CC
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
t20 SR
t21 SR
t22 CC
t24 CC
t26 CC
t28 CC
t38 CC
10 + tA
4 + tA
30 + 2tA
10 + 2tA
30 + tC
50 + tC
–
–
–
–
0
–
–
20 + tC
10 + tF
-10 + tF
0 + tF
-4 - tA
–
TCL -
–
ns
10+ tA
–
TCL -
–
ns
16+ tA
–
2TCL - 10
–
ns
+ 2tA
–
TCL -10
–
ns
+ 2tA
–
2TCL - 10
–
ns
+ tC
–
3TCL - 10
–
ns
+ tC
20 + tC
–
2TCL - 20 ns
+ tC
40 + tC
–
3TCL - 20 ns
+ tC
40 + tA +
tC
–
3TCL - 20 ns
+ tA + tC
50 + 2tA +
–
4TCL - 30 ns
tC
+ 2tA + tC
–
0
–
ns
26 + tF
10 + tF
–
–
–
–
10 - tA
–
2TCL - 14 ns
+ tF +
2tA1)
–
TCL - 10 ns
+ tF +
2tA1)
2TCL- 20
–
ns
+ tC
TCL -
10+ tF
–
ns
-10 + tF
–
ns
0 + tF
–
ns
-4 - tA
10 - tA ns
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