ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

XVI.4.12 - CLKOUT and READY

VDD = 5 V ± 10%

VSS = 0 V

Table 18 : CLKOUT and READY characteristics

TA = 0 to +70 °C

CL = 100 pF

Parameter

Symbol

Max. CPU Clock

= 25MHz

min.

max.

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to ALE falling edge

Synchronous READY setup time to CLKOUT

Synchronous READY hold time after CLKOUT

Asynchronous READY low time

t29 CC

t30 CC

t31 CC

t32 CC

t33 CC

t34 CC

t35 SR

t36 SR

t37 SR

40

14

10

–

–

0 + tA

14

4

58

40

2TCL

2TCL ns

–

TCL – 6

–

ns

–

TCL – 10

–

ns

4

–

4

ns

4

–

4

ns

10 + tA

–

0 + tA

14

10 + tA ns

–

ns

–

4

–

ns

–

2TCL +

–

ns

18

Asynchronous READY setup time 1)

t58 SR

14

–

14

–

ns

Asynchronous READY hold time 1)

t59 SR

4

–

4

–

ns

Async. READY hold time after RD, WR high

(Demultiplexed Bus) 2)

t60 SR

0

0 + 2tA +

0

TCL - 20 ns

tC + tF 2)

+ 2tA + tC

+ tF 2)

1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds

even more time for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle

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