ST10F163 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F163

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F163

Table 17 : Demultiplexed bus characteristics (continued)

Parameter

Symbol

Max. CPU Clock Variable CPU Clock

= 25MHz

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

Latched CS low to Valid Data In

Latched CS hold after RD, WR

Address setup to RdCS, WrCS (with RW-delay)

Address setup to RdCS, WrCS (no RW-delay)

RdCS to Valid Data In (with RW-delay)

RdCS to Valid Data In (no RW-delay)

RdCS, WrCS Low Time (with RW-delay)

RdCS, WrCS Low Time (no RW-delay)

Data valid to WrCS

Data hold after RdCS

Data float after RdCS (with RW-delay)

Data float after RdCS (no RW-delay)

Address hold after RdCS, WrCS

Data hold after WrCS

t39 SR

–

t41 CC 6 + tF

t82 CC 26 + 2tA

t83 CC 6 + 2tA

t46 SR

–

t47 SR

–

t48 CC 30 + tC

t49 CC 50 + tC

t50 CC 26 + tC

t51 SR

0

t53 SR

–

t68 SR

–

t55 CC

t57 CC

-10 + tF

6 + tF

40 + tC+

2tA

–

3TCL - 20 ns

+ tC + 2tA

–

TCL - 14

–

ns

+ tF

–

2TCL - 14

–

ns

+ 2tA

–

TCL -14

–

ns

+ 2tA

16 + tC

–

2TCL - 24 ns

+ tC

36 + tC

–

3TCL - 24 ns

+ tC

–

2TCL - 10

–

ns

+ tC

–

3TCL - 10

–

ns

+ tC

–

2TCL - 14

–

ns

+ tC

–

0

–

ns

20 + tF

0 + tF

–

–

–

2TCL - 20 ns

+ tF

–

TCL - 20 ns

+ tF

-10 + tF

–

ns

TCL - 14

–

ns

+ tF

1. RW-delay and tA refer to the following bus cycle.

2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore

address changes before the end of RD have no impact on read cycles

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