PIC18F2220/2320/4220/4320
FIGURE 26-12:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC18F4X20)
RE0/RD
RE1/WR
65
RD7:RD0
64
Note: Refer to Figure 26-5 for load conditions.
62
63
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
Param.
No.
Symbol
Characteristic
Min Max Units
62
TDTV2WRH Data in valid before WR ↑ or CS ↑
(setup time)
20 — ns
63
TWRH2DTI WR ↑ or CS ↑ to data–in invalid PIC18FXX20 20 — ns
(hold time)
PIC18LFXX20 35 — ns
64
TRDL2DTV RD ↓ and CS ↓ to data–out valid
— 80 ns
65
TRDH2DTI RD ↑ or CS ↓ to data–out invalid
10 30 ns
66
TIBFINH Inhibit of the IBF flag bit being cleared from
WR ↑ or CS ↑
— 3 TCY
Conditions
2003 Microchip Technology Inc.
DS39599C-page 331