PIC18LF2220-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF2220-I/SO
Microchip Technology
PIC18LF2220-I/SO Datasheet PDF : 388 Pages
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PIC18F2220/2320/4220/4320
FIGURE 26-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
83
78
79
80
79
78
SDO
MSb
bit 6 - - - - - -1
LSb
SDI
Note:
75, 76
MSb In
74
73
bit 6 - - - -1
Refer to Figure 26-5 for load conditions.
77
LSb In
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
71
TSCH
SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 —
71A
Single Byte
40
—
72
TSCL
SCK Input Low Time (Slave mode)
Continuous 1.25 TCY + 30 —
72A
Single Byte
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
PIC18LFXX20
45
76
TDOF
SDO Data Output Fall Time
—
25
77
TSSH2DOZ SS ↑ to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time (Master mode) PIC18FXX20
—
25
PIC18LFXX20
45
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
—
50
TSCL2DOV
PIC18LFXX20
100
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39599C-page 334
2003 Microchip Technology Inc.
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