PIC18LF2220-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF2220-I/SO
Microchip Technology
PIC18LF2220-I/SO Datasheet PDF : 388 Pages
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PIC18F2220/2320/4220/4320
FIGURE 26-16:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
PIC18LFXX20
45
76
TDOF
SDO Data Output Fall Time
—
25
77
TSSH2DOZ SS↑ to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
—
25
—
45
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
PIC18LFXX20
—
50
—
100
82
TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXX20
Edge
PIC18LFXX20
—
50
—
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2003 Microchip Technology Inc.
DS39599C-page 335
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