PIC18LF2220-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF2220-I/SO

28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2220/2320/4220/4320

TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100 THIGH Clock High Time

100 kHz mode

4.0

—

µs PIC18FXX20 must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

µs PIC18FXX20 must operate at a

minimum of 10 MHz

SSP module

1.5 TCY

—

101 TLOW Clock Low Time

100 kHz mode

4.7

—

µs PIC18FXX20 must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

µs PIC18FXX20 must operate at a

minimum of 10 MHz

SSP module

1.5 TCY

—

102 TR

SDA and SCL Rise 100 kHz mode

Time

400 kHz mode

—

1000

20 + 0.1 CB 300

ns

ns CB is specified to be from 10 to 400 pF

103 TF

SDA and SCL Fall

Time

100 kHz mode

—

300

400 kHz mode 20 + 0.1 CB 300

ns

ns CB is specified to be from 10 to 400 pF

90

TSU:STA Start Condition Setup 100 kHz mode

4.7

Time

400 kHz mode

0.6

—

µs Only relevant for Repeated

—

µs Start condition

91

THD:STA Start Condition Hold 100 kHz mode

4.0

Time

400 kHz mode

0.6

—

µs After this period, the first clock pulse is

—

µs generated

106 THD:DAT Data Input Hold Time 100 kHz mode

0

—

ns

400 kHz mode

0

0.9

µs

107 TSU:DAT Data Input Setup

100 kHz mode

250

Time

400 kHz mode

100

—

ns (Note 2)

—

ns

92

TSU:STO Stop Condition Setup 100 kHz mode

4.7

Time

400 kHz mode

0.6

—

µs

—

µs

109 TAA

Output Valid from

Clock

100 kHz mode

400 kHz mode

—

3500 ns (Note 1)

—

—

ns

110 TBUF Bus Free Time

100 kHz mode

4.7

400 kHz mode

1.3

—

µs Time the bus must be free before a

—

µs new transmission can start

D102 CB

Bus Capacitive Loading

—

400 pF

Note 1:

2:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT ≥ 250 ns,

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line

is released.

 2003 Microchip Technology Inc.

DS39599C-page 337

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