OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Timing Characteristics (continued)

Table 33B. OR2TxxB Sequential PFU Timing Characteristics

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Speed

Parameter

Symbol

-7

-8

Unit

Min

Max

Min

Max

S Input Requirements

Clock Low Time

TCL

1.7

—

1.4

—

ns

E Clock High Time

TCH

1.7

—

1.4

—

ns

Global S/R Pulse Width (GSRN)

TRW

1.7

—

1.4

—

ns

Local S/R Pulse Width

TPW

1.7

—

1.4

—

ns

IC Combinatorial Setup Times (TJ = 85 °C,

VDD = min):

D Four Input Variables to Clock

F4*_SET

1.0

—

0.8

—

ns

(A[4:0], B[4:0] to CK)

Five Input Variables to Clock

F5*_SET

1.0

—

0.8

—

ns

V (A[4:0], B[4:0] to CK)

E PFUMUX to Clock (A[4:0], B[4:0] to CK)

MUX_SET

1.3

—

1.3

—

ns

PFUMUX to Clock (C0 to CK)

C0MUX_SET

1.1

—

0.8

—

ns

PFUNAND to Clock (A[4:0], B[4:0] to CK)

ND_SET

1.0

—

0.8

—

ns

E U PFUNAND to Clock (C0 to CK)

C0ND_SET

0.8

—

0.7

—

ns

PFUXOR to Clock (A[4:0], B[4:0] to CK)

XOR_SET

1.3

—

1.3

—

ns

PFUXOR to Clock (C0 to CK)

C0XOR_SET

1.1

—

0.8

—

ns

D Data In to Clock (WD[3:0] to CK)

D*_SET

0.2

—

0.1

—

ns

IN Clock Enable to Clock (CE to CK)

CKEN_SET

1.0

—

0.8

—

ns

Local Set/Reset (synchronous) (LSR to CK)

LSR_SET

1.0

—

0.8

—

ns

Data Select to Clock (SEL to CK)

SELECT_SET

1.0

—

0.8

—

ns

Pad Direct In

PDIN_SET

0.0

—

0.0

—

ns

T T Combinatorial Hold Times (TJ = all, VDD = all):

Data In (WD[3:0] from CK)

D*_HLD

0.0

—

0.0

—

ns

Clock Enable (CE from CK)

CKEN_HLD

0.0

—

0.0

—

ns

C Local Set/Reset (synchronous) (LSR from CK)

LSR_HLD

0.0

—

0.0

—

ns

N Data Select (SEL from CK)

SELECT_HLD

0.0

—

0.0

—

ns

Pad Direct In Hold (DIA[3:0], DIB[3:0] to CK)1

PDIN_HLD

0.1

—

0.1

—

ns

All Others

—

0.0

—

0.0

—

ns

E Output Characteristics

O Sequential Delays (TJ = 85 °C, VDD = min):

L Local S/R (async) to PFU Out (LSR to Q[3:0])

LSR_DEL

2.2

—

1.8

—

ns

Global S/R to PFU Out (GSRN to Q[3:0])

GSR_DEL

1.4

—

1.0

—

ns

E C Clock to PFU Out (CK to Q[3:0])—Register

REG_DEL

1.0

—

1.0

—

ns

Clock to PFU Out (CK to Q[3:0])—Latch

LTCH_DEL

1.0

—

1.0

—

ns

Transparent Latch (WD[3:0] to Q[3:0])

LTCH_DDEL

1.7

—

1.4

—

ns

S DIS 1.The input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0.

Lattice Semiconductor

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