OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
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Description
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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ORCA Series 2 FPGAs
Data Sheet
November 2006
Timing Characteristics (continued)
Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.
Parameter
S Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
E Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
Symbol
Speed
-3
-4
-5
-6
-7 Unit
Min Max Min Max Min Max Min Max Min Max
TRC
3.6 — 2.7 — 2.4 — 2.3 — 2.0 — ns
MEM*_ADEL — 2.8 — 2.1 — 1.7 — 1.4 — 1.3 ns
MEM*_ASET 1.8 — 1.2 — 1.1 — 1.0 — 1.0 — ns
REG_DEL — 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns
IC D Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
V E Speed
Parameter
Symbol
-7
-8
Unit
E U Min
Max
Min
Max
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
TRC
1.9
—
1.8
—
ns
D Data Valid after Address (A[3:0], B[3:0] to F[3:0])
MEM*_ADEL
—
1.3
—
1.0
ns
IN Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
MEM*_ASET
0.9
—
0.8
—
ns
T Clock to PFU Out (CK to Q[3:0])—Register
REG_DEL
—
1.0
—
1.0
ns
TTRC
C N A[3:0], B[3:0]
ELE CO F[3:0]
MEM*_ADEL
Figure 55. Read Operation—Flip-Flop Bypass
5-3226(F).r4
S DIS A[3:0],B[3:0]
MEM*_ASET
CK
REG_DEL
Q[3:0]
Figure 56. Read Operation—LUT Memory Loading Flip-Flops
5-3227(F).r4
140
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