OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 38A. OR2CxxA and OR2TxxA Asynchronous Memory Read During Write, Clocking Data into Latch/
Flip-Flop (MA/MB Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
S Parameter
Symbol
-3
-4
-5
-6
-7
Unit
Min Max Min Max Min Max Min Max Min Max
E Setup Time (TJ = 85 °C, VDD = min):
Address to Clock (A[3:0], B[3:0] to CK)
MEM*_ASET 1.8 — 1.2 — 1.1 — 1.0 — 1.0 — ns
Write Enable (WREN) to Clock (A4/B4 to CK) MEM*_WRSET 4.4 — 3.8 — 3.4 — 3.1 — 3.0 — ns
Write-port Enable (WPE) to Clock (C0 to CK) MEM*_PWRSET 5.9 — 4.8 — 4.3 — 4.0 — 3.9 — ns
IC Data (WD[3:0] to CK)
MEM*_DSET 2.6 — 2.6 — 2.3 — 2.2 — 2.1 — ns
Hold Time (TJ = All, VDD = All): All
TH
0.0 — 0.0 — 0.0 — 0.0 — 0.0 — ns
D Clock to PFU Out (CK to Q[3:0])—Register
REG_DEL
— 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns
V Table 38B. OR2TxxB Asynchronous Memory Read During Write, Clocking Data into Latch/Flip-Flop
E (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
E +85 °C.
USpeed
D Parameter
Symbol
-7
-8
Unit
IN Min
Max
Min
Max
Setup Time (TJ = 85 °C, VDD = min):
Address to Clock (A[3:0], B[3:0] to CK)
MEM*_ASET
0.9
—
0.8
—
ns
T T Write Enable (WREN) to Clock (A4/B4 to CK) MEM*_WRSET
2.9
—
2.5
—
ns
Write-port Enable (WPE) to Clock (C0 to CK) MEM*_PWRSET
3.7
—
3.2
—
ns
Data (WD[3:0] to CK)
MEM*_DSET
2.0
—
1.7
—
ns
C Hold Time (TJ = all, VDD = all): All
TH
0.0
—
0.0
—
ns
SELDEISCON Clock to PFU Out (CK to Q[3:0])—Register
REG_DEL
—
1.0
—
1.0
ns
Lattice Semiconductor
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