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ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADE7880ACPZ-RL Datasheet PDF : 104 Pages
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Data Sheet
ADE7880
Table 32. Billable Registers
Address
0xE400
0xE401
0xE402
0xE403
Register
Name
AWATTHR
BWATTHR
CWATTHR
AFWATTHR
R/W1, 2
R
R
R
R
0xE404 BFWATTHR R
0xE405 CFWATTHR R
0xE406 Reserved
R
to
0xE408
0xE409 AFVARHR
R
0xE40A BFVARHR
R
0xE40B CFVARHR
R
0xE40C AVAHR
R
0xE40D BVAHR
R
0xE40E CVAHR
R
Bit
Length2
32
32
32
32
32
32
32
32
32
32
32
32
32
Bit Length
During
Communication2
32
32
32
32
32
32
32
32
32
32
32
32
32
Type2, 3
S
S
S
S
S
S
S
S
S
S
S
S
S
Default
Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Phase A total active energy accumulation.
Phase B total active energy accumulation.
Phase C total active energy accumulation.
Phase A fundamental active energy
accumulation.
Phase B fundamental active energy
accumulation.
Phase C fundamental active energy
accumulation.
Phase A fundamental reactive energy
accumulation.
Phase B fundamental reactive energy
accumulation.
Phase C fundamental reactive energy
accumulation.
Phase A apparent energy accumulation.
Phase B apparent energy accumulation.
Phase C apparent energy accumulation.
1 R is read, and W is write.
2 N/A is not applicable.
3 U is unsigned register, and S is signed register in twos complement format.
Table 33. Configuration and Power Quality Registers
Address
Register Name
Bit
R/W1 Length
Bit Length
During
Communication2
0xE500 IPEAK
R
32
32
0xE501 VPEAK
R
32
32
0xE502
0xE503
0xE504
STATUS0
STATUS1
AIMAV
R/W 32
R/W 32
R
20
32
32
32 ZP
0xE505 BIMAV
R
20
32 ZP
0xE506 CIMAV
R
20
32 ZP
0xE507
0xE508
0xE509
0xE50A
0xE50B
0xE50C
0xE50D
0xE50E
OILVL
OVLVL
SAGLVL
MASK0
MASK1
IAWV
IBWV
ICWV
R/W 24
R/W 24
R/W 24
R/W 32
R/W 32
R
24
R
24
R
24
32 ZP
32 ZP
32 ZP
32
32
32 SE
32 SE
32 SE
Type 3
U
U
U
U
U
U
U
U
U
U
U
U
S
S
S
Default
Value4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0xFFFFFF
0xFFFFFF
0x000000
0x00000000
0x00000000
N/A
N/A
N/A
Description
Current peak register. See Figure 58 and
Table 34 for details about its
composition.
Voltage peak register. See Figure 58 and
Table 35 for details about its
composition.
Interrupt Status Register 0. See Table 36.
Interrupt Status Register 1. See Table 37.
Phase A current mean absolute value
computed during PSM0 and PSM1
modes.
Phase B current mean absolute value
computed during PSM0 and PSM1
modes.
Phase C current mean absolute value
computed during PSM0 and PSM1
modes.
Overcurrent threshold.
Overvoltage threshold.
Voltage SAG level threshold.
Interrupt Enable Register 0. See Table 38.
Interrupt Enable Register 1. See Table 39.
Instantaneous value of Phase A current.
Instantaneous value of Phase B current.
Instantaneous value of Phase C current.
Rev. A | Page 85 of 104

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