ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7880ACPZ-RL
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADE7880ACPZ-RL Datasheet PDF : 104 Pages
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Data Sheet
ADE7880
Address
Register Name
Bit
R/W1 Length
Bit Length
During
Communication2
Default
Type3 Value4
0xEA0B to Reserved
0xEBFE
0xEBFF Reserved
8
8
8
8
0xEC00 LPOILVL
0xEC01 CONFIG2
R/W 8
8
R/W 8
8
U
0x07
U
0x00
Description
computations.
Reserved. These registers are always 0.
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the Serial Interfaces
section for details.
Overcurrent threshold used during
PSM2 mode. See Table 55 in which the
register is detailed.
Configuration register used during
PSM1 mode. See Table 56.
1 R is read, and W is write.
2 32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3 U is unsigned register, and S is signed register in twos complement format.
4 N/A is not applicable.
Table 34. IPEAK Register (Address 0xE500)
Bit
Mnemonic
Default Value
Description
23:0
24
25
26
31:27
IPEAKVAL[23:0]
IPPHASE[0]
IPPHASE[1]
IPPHASE[2]
0
0
0
0
00000
These bits contain the peak value determined in the current channel.
When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
These bits are always 0.
Table 35. VPEAK Register (Address 0xE501)
Bit
Mnemonic
Default Value
23:0
VPEAKVAL[23:0] 0
24
VPPHASE[0]
0
25
VPPHASE[1]
0
26
VPPHASE[2]
0
31:27
00000
Description
These bits contain the peak value determined in the voltage channel.
When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
These bits are always 0.
Table 36. STATUS0 Register (Address 0xE502)
Bit
Mnemonic
Default Value
0
AEHF
0
1
FAEHF
0
2
Reserved
0
3
FREHF
0
4
VAEHF
0
5
LENERGY
0
6
REVAPA
0
7
REVAPB
0
8
REVAPC
0
Description
When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed.
This bit is always 0.
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental
reactive energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 46).
When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 46).
When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The
sign itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 46).
Rev. A | Page 89 of 104
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