ADE7880
Data Sheet
Address
0xE50F
0xE510
0xE511
0xE512
0xE513
0xE514
0xE515
0xE516 to
0xE518
0xE519
0xE51A
0xE51B
0xE51F
0xE520
0xE521 to
0xE5FE
0xE5FF
0xE600
0xE601
0xE602
0xE603
0xE604 to
0xE607
0xE608
0xE609 to
0xE60B
0xE60C
0xE60D
0xE60E
0xE60F
0xE610
0xE611
0xE612
0xE613
0xE614
0xE615
0xE616
0xE617
0xE618
0xE700
0xE701
Register Name
INWV
VAWV
VBWV
VCWV
AWATT
BWATT
CWATT
Reserved
AVA
BVA
CVA
CHECKSUM
VNOM
R/W1
R
R
R
R
R
Bit
Length
24
24
24
24
24
R
24
R
24
R
24
R
24
R
24
R
24
R
32
R/W 24
Reserved
LAST_RWDATA32 R
32
PHSTATUS
ANGLE0
R
16
R
16
ANGLE1
R
16
ANGLE2
R
16
Reserved
PHNOLOAD
Reserved
R
16
LINECYC
ZXTOUT
COMPMODE
Gain
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
BPHCAL
CPHCAL
PHSIGN
CONFIG
R/W 16
R/W 16
R/W 16
R/W 16
R/W 16
R/W 16
R/W 16
R/W 16
R/W 10
R/W 10
R/W 10
R
16
R/W 16
MMODE
ACCMODE
R/W 8
R/W 8
Bit Length
During
Communication2
32 SE
32 SE
32 SE
32 SE
32 SE
Type 3
S
S
S
S
S
32 SE
S
32 SE
S
32 SE
S
32 SE
S
32 SE
S
32 SE
S
32
U
32 ZP
S
32
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16
U
16 ZP
U
16 ZP
U
16 ZP
U
16
U
16
U
8
U
8
U
Rev. A | Page 86 of 104
Default
Value4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x000000
Description
Instantaneous value of neutral current.
Instantaneous value of Phase A voltage.
Instantaneous value of Phase B voltage.
Instantaneous value of Phase C voltage.
Instantaneous value of Phase A total
active power.
Instantaneous value of Phase B total
active power.
Instantaneous value of Phase C total
active power.
N/A
N/A
N/A
0xAFFA63B9
0x000000
N/A
N/A
N/A
N/A
N/A
N/A
0xFFFF
0xFFFF
0x01FF
0x0000
0x0EA0
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
0x0002
0x1C
0x80
Instantaneous value of Phase A
apparent power.
Instantaneous value of Phase B
apparent power.
Instantaneous value of Phase C
apparent power.
Checksum verification. See the
Checksum Register section for details.
Nominal phase voltage rms used in the
alternative computation of the
apparent power.
These addresses should not be written
for proper operation.
Contains the data from the last successful
32-bit register communication.
Phase peak register. See Table 40.
Time Delay 0. See the Time Interval
Between Phases section for details.
Time Delay 1. See the Time Interval
Between Phases section for details.
Time Delay 2. See the Time Interval
Between Phases section for details.
These address should not be written for
proper operation.
Phase no load register. See Table 41.
These address should not be written for
proper operation.
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation-mode register. See Table 42.
PGA gains at ADC inputs. See Table 43.
CFx configuration register. See Table 44.
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A. See Table 45.
Phase calibration of Phase B. See Table 45.
Phase calibration Phase of C. See Table 45.
Power sign register. See Table 46.
ADE7880 configuration register.
See Table 47.
Measurement mode register. See Table 48.
Accumulation mode register.