ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6444IRGCT

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

www.ti.com

APPLICATION INFORMATION (continued)

COARSE GAIN AND PROGRAMMABLE FINE GAIN

ADS644X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain

mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain

setting, the analog input full-scale range scales proportionally, as listed in Table 21.

The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as

seen in Figure 10 and Figure 11). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain

also, SFDR improvement is achieved, but at the expense of SNR (there is about 1dB SNR degradation for every

1dB of fine gain).

So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get

best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the

SFDR improvement is significant with marginal degradation in SINAD.

The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18) and <FINE GAIN>

(refer to Table 17). Note that the default gain after reset is 0 dB.

GAIN, dB

0

3.5

1

2

3

4

5

6

Table 21. Full-Scale Range Across Gains

TYPE

Default (after reset)

Coarse setting (fixed)

Fine setting (programmable)

FULL-SCALE, VPP

2

1.34

1.78

1.59

1.42

1.26

1.12

1.00

CLOCK INPUT

The ADS644X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),

with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

VCM using internal 5-kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for

sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 90 and Figure 92).

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