ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADS6444IRGCT Datasheet PDF : 75 Pages
| |||
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
www.ti.com
DIGITAL OUTPUT INTERFACE
The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of
these options can be easily programmed using either parallel pins or the serial interface.
The output interface options are:
• 1-Wire, 1× frame clock, 14× and 16× serialization with DDR bit clock
• 2-Wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options
INTERFACE OPTIONS
1-Wire
2-Wire
2-Wire
DDR Bit
clock
DDR Bit
clock
SDR Bit
clock
14× Serialization
16× Serialization
14× Serialization
16× Serialization
14× Serialization
16× Serialization
MAXIMUM
RECOMMENDED
SAMPLING
FREQUENCY,
MSPS
65
65
125
125
65
65
BIT CLOCK
FREQUENCY,
MHZ
455
520
437.5
500
455
520
FRAME CLOCK
FREQUENCY, MHZ
65
65
62.5
125
65
65
SERIAL DATA
RATE, Mbps
910
1040
875
1000
910
1040
Each interface option is described in detail in the following sections.
1-WIRE INTERFACE - 14× AND 16× SERIALIZATION WITH DDR BIT CLOCK
Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at
the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of
every frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data
rate is 14 × sample frequency (14× serialization) and 16 × sample frequency (16× serialization).
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