ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6444IRGCT

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

www.ti.com

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

Input Clock,

CLKP/M

Freq = Fs

Frame Clock,

FCLKP

Freq = 1 ´ Fs

Bit Clock – DDR,

DCLKP/M

Freq = 7 ´ Fs

Output Data

DA, DB, DC, DD

Data Rate = 14 ´ Fs

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11) (D12) (D13) (D0) (D1)

Bit Clock – DDR,

DCLKP/M

Freq = 8 ´ Fs

Output Data

DA, DB, DC, DD

Data Rate = 16 ´ Fs

0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9) (D10) (D11) (D12) (D13) (0)

D0 0 0

(0) (D0) (D1)

Sample N

Sample N + 1

Data Bit in MSB First Mode

D13

(D2)

Data Bit in LSB First Mode

(1) In 16-Bit serialization, two zero bits are padded to the 14-bit ADC data on the MSB side.

T0225-02

Figure 93. 1-Wire Interface

2-WIRE INTERFACE - 16× SERIALIZATION WITH DDR/SDR BIT CLOCK

The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16× serialization, two zero

bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output

over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock

cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent

over the 2 wires as byte-wise or bit-wise or word-wise.

Using the 16× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without

requiring any modification to the receiver capture logic design.

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