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ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
VCM
CLKP
5 kW
VCM
5 kW
CLKM
ADS6xxx
S0166-04
Figure 89. Internal Clock Buffer
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS6xxx
S0167-05
Figure 90. Differential Clock Driving Circuit
Figure 91 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
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